The simulation will be performed with the designated root module at the top-level. The simulator internally expands any module instances in your circuit. Since the path you take to get to a module is significant to the simulator, you cannot jump directly to submodules but must "navigate" your way to them by selecting a module at the current level and by opening it using the menu or the '>' keyboard command. You can leave a module you are in with the '<' keyboard command.
Gate and wire names in sub-modules are referenced by prepending a dot-separated "path" of module instance names. For instance, suppose there are two instances of a module named "foo" in the root module with instance names "g1" and "g2". Now suppose the "foo" module contains a wire named "w1". These wire names are referenced by the simulator as "g1.w1" and "g2.w1" to distinguish the two instances.
TkGate is an event-driven simulator. Time is measured in discrete units called "epochs". Each gate has a delay of a certain number of epochs. Some complex gates have multiple delay constants. In addition, some gates such as registers and memories have additional delay parameters which affect internal state changes.
The basic simulator commands are:
Function | Button | Description |
---|---|---|
Run | Enters continuous simulation mode. The simulation will continue as long as there are events in the event queue. If there are any clock gates in your circuit, this will mean the simulation will continue indefinately. If the circuit is combinational, the simulation will continue until the circuit reaches quiescence. | |
Pause | Causes a continuously running simulation to stop. | |
Step Epoch | Causes the simulation to advance a fixed number of epochs. The number of epochs to advance can be set on the simulation options menu. You can also invoke this command with the spacebar. | |
Step Cycle | Causes the simulation to advance to the rising edge of a clock. You can set the number of clock cycles to simulate and the number of epochs past the designated cycle to step (to allow time for registers to change value). The default is to trigger on any clock, but you can designate a specific clock in the simulator options menu. You can also invoke this command with the tab key. | |
End Simulation | Causes the simulation to be terminated and all probes to be deleted. |
Other simulator commands will be discussed in the following sections.
The simulator options are:
Symbol | Scope | Description |
---|---|---|
0 | ![]() |
Logic 0 |
1 | ![]() |
Logic 1 |
x | ![]() |
Unknown |
z | ![]() |
Floating |
L | ![]() |
Low (the signal is either floating or zero) |
H | ![]() |
High (the signal is either floating or one) |
To display the value of a signal in a circuit, click and hold the
mouse button on a wire. This will display the current value driven on
the wire in verilog syntax. The value will disappear when you release
the mouse button. This feature can be used both when the simulator is
paused and when it is in continuous simulation mode. When the
simulator is in continuous simulation mode, the value displayed will
be the value at the time the mouse button was first pressed.
To set a permanent probe on a signal, double click on a wire. This
will add or remove a probe. When a probe is set on a wire, its value
will be continuously displayed in the scope window. The values of
multi-bit signals will be displayed as hex numbers. You can use the
scroll bars to set move the scope to display early times or you can
use the '>' and '<' keyboard commands to expand or compress the time
scale.
To print a scope trace, choose the "Print..." option from the "File"
menu on the scope window, or use the keyboard shortcut "Ctl-s p". The
dialog box shown here will be displayed. The left half of the dialog
box is the same as the left half of the dialog box used to print circuits. The
right half includes options for selecting the time range to print and
the scale factor to use. Beware that simulation traces can grow very
large, very quickly, especially when you use the continuous simulation
mode. An estimate of the number of pages needed for each trace you
have set is displayed to help you set parameters.
To send a character to a tty element, drive the RD input with the ascii code of the character to transmit and wait for the DTR output to go high. Next assert the DSR signal (positive high). The character will be transmitted on the positive edge of the DSR signal. You must then unassert the DSR signal so that the next character can be sent.
To receive a character, first unassert the CTS signal and wait for the
RTS signal to go high. You can then read the value on the TD ouput of
the tty. Once you have read the value, assert the CTS signal to
indicate that you have received the character.
Button |
---|
When you add or edit a breakpoint, a breakpint editing dialog box such as the one shown here will be displayed. Enter or edit the breakpoint condition and hit OK. Currently, only a limited number of breakpoint types can be used. Only a single signal can be compared with a constant using a single relational operator. The relational operators are the standard relational operators used in C. The value must be a verilog syntax constant. Alternitively, you can simply type a signal name to break when the signal becomes non-zero, or a sginal name prepended with the '!' operator to break when the signal becomes zero.
Function | Button | Description |
---|---|---|
Load Memory... | Load memories from the selected file. If a memory gate is selected, that memory will be the default memory to load. If the memory file contains one or more "memory" keywords, the specified memory(ies) will be loaded with the contents of the file. When loading a file, the current directory, the directory of the current circuit file, and the user's home directory will be searched. | |
Dump Memory... | Dumps the contents of the selected memory to a file. |
100/ e1 f0 0 0 e1 e0 0 0 108/ 81 0 0 0 12 1 bd 0 110/ e 1 e1 d0 dc 7 85 0 118/ 6f 6 81 0 0 0 4e 4 120/ 69 f0 2 0 85 0 64 0 128/ 81 0 0 0 26 4 69 f0 130/ 2 0 ed 0 60 6 62 6 138/ ed 0 5e 6 1 0 85 0The address at the beginning of the line specifies the address at which to begin storing values. Values are stored sequentially from the specified address one word at a time for the rest of the line.
If there is no "memory" keyword in the memory file, the selected memory gate will be loaded. The memory keyword requires a single argument specifing the name of a memory. For example:
memory memory.m1 100/ e1 f0 0 0 e1 e0 0 0 108/ 81 0 0 0 12 1 bd 0will load the memory "m1" in the instance named "memory" which is a submodule of the root module. In order to assist in creating memory files, you can use gmac to compile microcode and macrocode descriptions into TkGate-compatable memory files.
For RAM memories, the contents of the loaded memory are frozen until first time the write line transitions to a stable value (logic 0 or 1). This prevents the data loaded from being destroyed due to unknown values on the write and address lines until the circuit has time to intitilize these signals.
Button |
---|
You can also arrange for simulation scripts to be automatically
executed when you start the simulator either by specifying a
simulation script in the simulation options
dialog box, or by adding simulation scripts as circuit options. The following
simulation script commands are recognized. Arguments specified
between "?" characters denote optional arguments.
Command | Description |
---|---|
include "file" | Includes the specified file as if its contents appear here in the simulation script. |
step n | Steps the specified number of epochs. |
clock(+/-) ?[name]? n ?+m? | Step n clock steps. If the character after "clock" is a "+" stepping will be on positive clock edges. If the character is a "-" the stepping will be on negative clock edges. If name is specified, only edges on that clock will be used. If m is specified, then the simulator will step that number of epochs after the final clock edge. |
run | Put the simulator into continuous simulation mode. This command will block until a breakpoint is hit, or until you press the pause button. |
break ?[name]? cond | Sets the breakpoint cond which must have the syntax described in the section on breakpoints. If a name is specifed in square brackets. This breakpoint will be assigned a symbolic name which can be referenced to deleted the breakpoint later. If no name is specified, then it will not be possible to remove the breakpoint from a simulation script. |
delete [name] | Deletes the specified breakpoint. Only breakpoints set through a simulation script and assigned a symbolic name can be deleted. |
set name value | Sets the value of a switch or dip switch. Name should specify the full path of a switch or dip switch, and value should be a verilog syntax constant. |
probe name | Sets a probe on signal name. The name should be specified as a full path. |
unprobe name | Removes the probe on signal name. The name should be specified as a full path. |
load ?name? "file" | Load memories from a file. If you specify a memory name, that memory will be the default memory. |
dump name "file" | Dumps the contents of the specified memory to a file. |
delay mux<S-Z> = 20 delay mux<I-Z> = 10The first command sets the delay from the S input to the output to 20, and the second command sets the delay from any of I inputs to the output to 10. You can also specify '*' for the delay parameter to set all delays for a gate type to the same value. Comments in a delay file are indicated by lines starting with '#'.
A current limitation of TkGate delays is that it is not possible to
specify delay as a function of the number of inputs, or of port bit
widths. For example, a 4-bit adder will have the same delay as a
32-bit adder. Also, inverting input and output are not considered in
calculating delay.
Gate Type | Parameter | Default | Description |
---|---|---|---|
and | I-Z | 5 | Delay from input to output. |
or | I-Z | 5 | Delay from input to output. |
xor | I-Z | 5 | Delay from input to output. |
buf | I-Z | 3 | Delay from input to output. |
bufif1 | E-Z | 3 | Delay from enable to output. |
I-Z | 5 | Delay from data input to output. | |
nmos | I-Z | 3 | Delay from data input to output. |
G-Z | 2 | Delay from gate to output. | |
pmos | I-Z | 3 | Delay from data input to output. |
G-Z | 2 | Delay from gate to output. | |
add | A/B-S | 30 | Delay from operand input to sum. |
A/B-CO | 35 | Delay from operand input to carry out. | |
CI-S | 35 | Delay from carry in to sum. | |
CI-CO | 40 | Delay from carry in to carry out. | |
register | setup | 10 | Time before clock edge data-in must be stable. |
hold | 10 | Time after clock edge data-in must remain stable. | |
CK-Q | 20 | Time from clock edge until output changes. | |
mux | S-Z | 20 | Delay from select line to output. |
I-Z | 10 | Delay from data input to output. | |
demux | E-Z | 10 | Delay from enable line to output. |
I-Z | 25 | Delay from data input to output. | |
mult | A/B-Z | 60 | Delay from operand input to output. |
div | A/B-Q | 80 | Delay from operand input to quotient. |
A/B-R | 80 | Delay from operand input to remainder. | |
ram | OE-D | 10 | Delay from output enable to data-out. |
CS-D | 10 | Delay from chip select to data out. | |
A-D | 70 | Delay from the address line to the data out. | |
addr_setup | 10 | Time before write is asserted that address must be stable. | |
data_setup | 10 | Time before write is asserted that data-in must be stable. | |
addr_hold | 10 | Time after write is unasserted that address must remain stable. | |
data_hold | 10 | Time after write is unasserted that data-in must remain stable. | |
rom | OE-D | 10 | Delay from output enable to data-out. |
A-D | 50 | Delay from address to data-out. | |
tty | TR | 150 | Time to transmit a character. |
RTS_UP | 2 | Time after transmition is complete before RTS line is raised. | |
RTS_DN | 8 | Time after DSR is asserted that RTS will fall. | |
RD | 150 | Time to read a character. | |
DTR_UP | 2 | Time after character is received that DTR will be raised. | |
DTR_DN | 2 | Time after CTS is asserted that DTR will fall. | |
lshift | S-Z | 10 | Delay from shift select to output. |
I-Z | 12 | Delay from data-in to output. | |
rshift | S-Z | 10 | Delay from shift select to output. |
I-Z | 12 | Delay from data-in to output. | |
arshift | S-Z | 10 | Delay from shift select to output. |
I-Z | 12 | Delay from data-in to output. | |
roll | S-Z | 10 | Delay from shift select to output. |
I-Z | 12 | Delay from data-in to output. |